RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Document Table of Contents Transmit Port-Write Registers

Table 131.  Tx Port Write Control — Offset: 0x10200
Field Bits Access Function Default
LARGE_DESTINATION_ID (MSB) [31:24] RW/RO MSB of the Destination ID if the system supports 16-bit device ID.

Reserved if the system does not support 16-bit device ID.

DESTINATION_ID [23:16] RW Destination ID. 8'h00
RSRV [15:8] RO Reserved. 8'h00
PRIORITY [7:6] RW Request packet’s priority. 2’b11 is not a valid value for the PRIORITY field. Any attempt to write 2’b11 to this field is overwritten with 2’b10. 2'b00
SIZE [5:2] RW Packet payload size in number of double words. If set to 0, the payload size is single word. If size is set to a value larger than 8, the payload size is 8 double words (64 bytes). 4'h0
RSRV [1] RO Reserved. 1'b0
PACKET_READY [0] RW Write 1 to start transmitting the port-write request. This bit is cleared internally after the packet has been transferred to the Transport layer to be forwarded to the Physical layer for transmission. 1'b0
Table 132.  Tx Port Write Status — Offset: 0x10204
Field Bits Access Function Default
RSRV [31:0] RO Reserved. 32'h0
Table 133.  Tx Port Write Buffer n — Offset: 0x10210 – 0x1024C
Field Bits Access Function Default
PORT_WRITE_DATA_n [31:0] RW Port-write data. This buffer is implemented in memory and is not initialized at reset. 32'hx