RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.2.4. Clock Rate Relationships in the RapidIO II IP Core

The RapidIO v2.2 specification specifies baud rates of 1.25, 2.5, 3.125, 5.0, and 6.25 Gbaud.

Table 12.  Clock Frequencies in the RapidIO II IP CoreFollowing are the clock rates in the different RapidIO II IP core variations, showing the relationship between baud rate, default transceiver reference clock frequency, and Avalon system clock frequency.
Baud Rate (Gbaud) Default reference clock frequency (MHz)10 Avalon system clock Frequency (MHz)11
1.25 156.25 31.25
2.5 156.25 62.5
3.125 156.25 78.125
5.0 156.25 125.0
6.25 156.25 156.25
10 The reference clock is called tx_pll_refclk by default.
11 The Avalon system clock is called sys_clk by default. It runs at 1/40 the frequency of the maximum baud rate you configure in the RapidIO II parameter editor, irrespective of the baud rate you program in software. You must drive sys_clk and the reference clock from the same clock source.

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