RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Document Table of Contents
Give Feedback Port-Write Reception

When the RapidIO II IP core Maintenance module receives a MAINTENANCE port-write request packet (ftype has the value of 4’b1000 and ttype has the value of 4’b0100) from the Transport layer, it extracts information from the packet header and uses the information to write to registers Rx Port Write Control through Rx Port Write Buffer. The Maintenance module extracts information from the following fields:
  • wrsize and wdptr — the values in the wrsize and wdptr packet fields determine the value of the PAYLOAD_SIZE field in the Rx Port Write Status register.
  • payload — the Maintenance module copies the value of the payload packet field to the Rx Port Write Buffer starting at register address 0x10260. This buffer holds a maximum of 64 bytes.
While the IP core is writing the payload to the buffer, it holds the PORT_WRITE_BUSY bit of the Rx Port Write Status register asserted. After the payload is completely written to the buffer, if you have set the RX_PACKET_STORED bit of the Maintenance Interrupt Enable register, the IP core asserts the interrupt signal mnt_mnt_s_irq on the Register Access interface to alert your system of the port-write request.