RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.3.4.5. Receiving a Doorbell Message

When the Doorbell module receives a DOORBELL request packet from the Transport layer module, the module stores the request in an internal buffer and generates an interrupt on the DOORBELL Avalon-MM slave interface—asserts the drbell_s_irq signal—if this interrupt is enabled.

The corresponding interrupt status bit is set every time a DOORBELL request packet is received and resets itself when the Rx FIFO is empty. Software can clear the interrupt status bit by writing a 1 to this specific bit location of the Doorbell Interrupt Status register.

The RapidIO II IP core generates an interrupt when it receives a valid response packet and when it receives a request packet. Therefore, when user logic receives an interrupt (the drbell_s_irq signal is asserted), you must check the Doorbell Interrupt Status register to determine the type of event that triggered the interrupt.

If the interrupt is not enabled, user logic must periodically poll the Rx Doorbell Status register to check the number of available messages before retrieving them from the Rx doorbell buffer.

The Doorbell module generates and sends appropriate Type 13 response packets for all the DOORBELL messages it receives. The module generates a response with the following status, depending on its ability to process the message:
  • With DONE status if the received DOORBELL packet can be processed immediately.
  • With RETRY status to defer processing the received message when the internal hardware is busy, for example when the Rx doorbell buffer is full.

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