RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.5. Physical Layer

The Physical layer has the following features:
  • Port initialization
  • Transmitter and receiver with the following features:
    • One, two, or four lane high-speed data serialization and deserialization
    • Clock and data recovery (receiver)
    • 8B10B encoding and decoding
    • Lane synchronization (receiver)
    • Packet/control symbol assembly and delineation
    • Packet cyclic redundancy code (CRC) (CRC-16) generation and checking
    • Control symbol CRC-13 generation and checking
    • Error detection
    • Pseudo-random IDLE2 sequence generation
    • IDLE2 sequence removal
    • Scrambling and descrambling
  • Software interface (status/control registers)
  • Flow control (ackID tracking)
  • Time-out on acknowledgments
  • Order of retransmission maintenance and acknowledgments
  • ackID assignment through software interface
  • ackID synchronization after reset
  • Error management
  • Clock decoupling
  • FIFO buffer with level output port
  • Four transmission queues and four retransmission queues to handle packet prioritization
Figure 37. Physical Layer High Level Block Diagram

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