RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Document Table of Contents Link-Request Reset-Device Signals

Table 58.  Link-Request Reset-Device Signals
Signal Direction Description
send_link_request_reset_device Input Change the value of this signal to indicate the RapidIO II IP core should transmit five link-request reset-device control symbols.

Await assertion of the sent_link_request_reset_device signal before you toggle this signal again. If you toggle this signal before you see the sent_link_request_reset_device confirmation from the previous change of value, the RapidIO II IP core behavior is undefined.

link_req_reset_device_received Output Asserted for one sys_clk cycle when four valid link-request reset-device control symbols in a row are received.

The assertion of this signal does not automatically reset the IP core. However, your design can implement logic to reset the IP core in response to the assertion of this signal. For example, you could implement a direct connection from this signal to a reset controller for the IP core and the transceiver, or implement logic to write to a register that reset software polls.

sent_link_request_reset_device Output Indicates the RapidIO II IP core has queued a series of five link-request reset-device control symbols for transmission.