RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.6.2.6. Input/Output Avalon-MM Master

The I/O Avalon-MM master module processes the request packets that it receives and generates response packets when required. Anomalies are reported through one or both of the following two channels:
  • Standard error management registers
  • Response packets with ERROR status
Standard Error Management Registers
The following two standard defined error types can be declared by the I/O Avalon-MM master module. The corresponding bits are then set and the required packet information is captured in the appropriate error management registers.
  • Unsupported Transaction is declared when a request packet carries a transaction type that is not supported in the Destination Operations CAR, whether an ATOMIC transaction type, a reserved transaction type, or an implementation defined transaction type.
  • Illegal Transaction Decode is declared when a request packet for a supported transaction is too short or if it contains illegal values in some of its fields such as in these examples:
    • Request packet with priority = 3.
    • NWRITE, NWRITE_R, or SWRITE request packets without payload.
    • NWRITE or NWRITE_R request packets with reserved wrsize and wdptr combination.
    • NWRITE, NWRITE_R, SWRITE, or NREAD request packets for which the address does not match any enabled address mapping window.
    • NREAD request packet with payload.
    • NREAD request with rdsize that is not an integral number of transfers on all byte lanes. (The Avalon-MM interface specification requires that all byte lanes be enabled for read transfers. Therefore, Read Avalon-MM master modules do not have a byteenable signal).
    • Payload size does not match the size indicated by the rdsize or wrsize and wdptr fields.
Response Packets with ERROR Status

An ERROR response packet is sent for NREAD and NWRITE_R and Type 5 ATOMIC request packets that cause an Illegal Transaction Decode error to be declared. An ERROR response packet is also sent for NREAD requests if the iom_rd_wr_readresponse input signal is asserted through the final cycle of the Avalon-MM read transfer.

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