RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.2.2.2. LP-Serial Lane n Status 0

Table 100.  LP-Serial Lane n Status 0 — 0x210, 0x230, 0x250, 0x270
Field Bits Access Function Default
Port Number [31:24] RO The number of the port within the IP core to which the lane is assigned. The RapidIO II IP core implements only a single RapidIO port, so this field always has the value of 0. 8'b0
Lane Number [23:20] RO The number of the lane in the port. 4'hn
Transmitter Type [19] RO Transmitter type:
  • 1’b0: Short run
  • 1’b1: Long run.
This value is identical for all lanes of the port.
0
Transmitter Mode [18] RW Transmitter operating mode:
  • 1’b0: Short run
  • 1’b1: Long run
The value in this field is identical for all lanes and is identical to the value of the Transmitter Type field. The value in this field does not affect the physical transceiver. Software must modify this bit if relevant physical transceiver properties change.
0
Receiver Type [17:16] RO Receiver type:
  • 2’b00: Short run
  • 2’b01: Medium run
  • 2’b10: Long run
  • 2’b11: Reserved.
This value is identical for all lanes of the port.
0
Receiver Input Inverted [15] RO Indicates that the lane receiver has detected that the polarity of its input signal is inverted, and has inverted the receiver input to correct the polarity. A value of 1’b0 indicates the receiver input is not inverted. The RapidIO II IP core does not support automatic detection of inverted inputs, and this field always has the value of 0. 1’b0
Receiver Trained [14] RO If the lane receiver controls any transmit or receive adaptive equalization, this bit indicates whether all of the adaptive equalizers that this lane controls are now trained. The value of this field is the value in the Receiver trained bit in the CS field the lane transmits.
  • 1’b0: The lane receiver controls one or more adaptive equalizers and at least one of these adaptive equalizers is not trained.
  • 1’b1: The lane receiver controls no adaptive equalizers, or all of the adaptive equalizers it controls are trained.
1’b0
Receiver Lane Sync [13] RO Indicates the state of the lane n lane_sync signal.
  • 1’b0: lane_sync is FALSE
  • 1’b1: lane_sync is TRUE
1’b0
Receiver Lane Ready [12] RO Indicates the state of the lane n lane_ready signal.
  • 1’b0: lane_ready is FALSE
  • 1’b1: lane_ready is TRUE
1’b0
8B10B_DEC_ERR [11:8] RC Number of 8B10B decoding errors detected on this lane since this register bit was last read. The value saturates at 0xF (it does not roll over). Reading the register resets this field to the value of 0. 4’h0
Lane_sync State Change [7] RC Indicates the state of the lane_sync signal for this lane has changed since this bit was last read. Reading the register resets this bit to the value of 1’b0. This bit provides an indication of the burstiness of the transmission errors that the lane receiver detected. 1’b0
Rcvr_trained State Change [6] RO Indicates the state of the rcvr_trained signal for this lane has changed since this bit was last read. Reading the register resets this bit to the value of 1’b0. A change in the signal value indicates that the training state of the adaptive equalization under the control of this receiver has changed; frequent changes indicate a problem on the lane. 1’b0
RSRV [5:4] RO Reserved. 2'b00
Status 1 CSR Implemented [3] RO Indicates whether the RapidIO implementation includes the Lane n Status 1 CSR for the current lane n. The RapidIO II IP core implements this register, so this bit always has the value of 1’b1. 1'b1
Status 2–7 CSRs Implemented [2:0] RO Number of implementation-specific Lane n Status m CSRs for the current lane n. The RapidIO II IP core implements the Lane n Status 2, Lane n Status 3, and Lane n Status 4 CSRs, so this field always has the value of 2’b011. 3'b011

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