RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.1. Memory Map

Table 77.  RapidIO II IP Core Memory Map Ranges
Address Range Name Module
0x00 – 0x3C Capability registers (CARs) Standard registers
0x40 – 0x6F Command and Status registers (CSRs) Standard registers
0x100 – 0x15F LP-Serial Extended Features block Physical layer
0x200 – 0x27F LP-Serial Lane Extended Features block Physical layer
0x300 – 0x36F Error Management Extensions Extended Features block Standard registers
Implementation-Defined Space: 0x10080 – 0x107FF
0x10080 – 0x1029F Maintenance module registers Maintenance module
0x10300 – 0x103FC I/O Logical layer Master module registers I/O Logical layer Master module
0x10400 – 0x10510 I/O Logical layer Slave module registers I/O Logical layer Slave module
0x10600 – 0x10624 Doorbell module registers Doorbell module
0x10700 – 0x107FF Reserved
Note: Bit numbering for register fields in the RapidIO II IP core is reversed from the bit numbering in the register descriptions in the RapidIO Interconnect Specification v2.2.