RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.1.7. I/O Logical Layer Master Module Registers Memory Map6.3.4.1. I/O Logical Layer Master Module Registers Memory Map

Table 84.  Table 137.  I/O Logical layer Master Module Registers Memory Map
Address Register
0x10300 I/O Master Window 0 Base
0x10304 I/O Master Window 0 Mask
0x10308 I/O Master Window 0 Offset
0x1030C Reserved
0x10310 – 0x103F8 (with gaps) I/O Master Windows 1–15
0x103DC I/O Master Interrupt
0x103FC I/O Master Interrupt Enable

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