RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.2.2.4. LP-Serial Lane n Status 2

Table 102.  LP-Serial Lane n Status 2 — 0x218, 0x238, 0x258, 0x278
Field Bits Access Function Default
RSRV [31:30] RO Reserved. 2'b00
Process CMD automatically [29] RO When set, enables automatic processing of CS field values received in the IDLE2 sequence. The RapidIO II IP core does not yet implement this feature. 1'b0
RSRV [28:0] RO Reserved. 29'b0

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