RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.2.3. Recovered Data Clock

The clock and data recovery block (CDR) in the transceiver recovers this clock, rx_clkout, from the incoming RapidIO data. The RapidIO II IP core provides this output clock as a convenience. You can use it to source a system-wide clock with a 0 ppm frequency difference from the clock used to transmit the incoming data.

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