RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.3.6.11. Port 0 Error Rate Enable

Table 163.  Port 0 Error Rate Enable CSR — Offset: 0x344
Field Bits Access Function Default
RSRV [31] RO Reserved for this implementation. 1'b0
RSRV [30:24] RO Reserved. 7'h0
RSRV [23] RO Enable error rate counting of corresponding error. 1'b0
Received corrupt control symbol enable [22] RW Enable error rate counting of corresponding error. 1'b0
Received ACK control symbol with unexpected ackID enable [21] RW Enable error rate counting of corresponding error. 1'b0
Received packet-not-accepted control symbol enable [20] RW Enable error rate counting of corresponding error. 1'b0
Received packet with unexpected ackID enable [19] RW Enable error rate counting of corresponding error. 1'b0
Received packet with bad CRC enable [18] RW Enable error rate counting of corresponding error. 1'b0
Received packet exceeding max size enable [17] RW Enable error rate counting of corresponding error. 1'b0
Received illegal or invalid character enable [16] RW Enable error rate counting of corresponding error. 1'b0
Received data character in IDLE1 sequence enable [15] RW Reserved for this implementation, The RapidIO II IP core does not support the IDLE1 sequence. 1'b0
Loss of descrambler synchronization enable [14] RW Enable error rate counting of corresponding error. 1'b0
RSRV [13:6] RO Reserved. 7'h0
Non-outstanding ackID enable [5] RW Enable error rate counting of corresponding error. 1'b0
Protocol error enable [4] RW Enable error rate counting of corresponding error. 1'b0
RSRV [3] RO Reserved for this implementation. 1'b0
Delineation error enable [2] RW Enable error rate counting of corresponding error. 1'b0
Unsolicited ACK control symbol enable [1] RW Enable error rate counting of corresponding error. 1'b0
Link timeout enable [0] RW Enable error rate counting of corresponding error. 1'b0

Did you find the information on this page useful?

Characters remaining:

Feedback Message