RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Document Table of Contents

7.2.5. NWRITE_R Transactions

To perform NWRITE_R operations, one register in the IP core must be reconfigured as shown below:
Table 184.  NWRITE_R Transactions
Module Register Address Register Name Description Value
rio 0x1040C Input/Output Slave Mapping Window 0 Control Sets the DESTINATION_ID for outgoing transactions to the value 0x55 or 0x5555, depending on the device ID width of the sister_rio. This value matches the base device ID of the sister_rio module. Enables NWRITE_R operations. 32'h00CD_0001 or 32'hCDCD_0001

With these settings, any write operation presented across the Input/Output Avalon-MM slave module's Avalon-MM write interface is translated to a RapidIO NWRITE_R transaction. The Avalon-MM write address must map to the range specified for the I/O Slave window 0.

To initialize testing of the new NWRITE_R completion indication feature, the test first checks that the PENDING_NWRITE_RS field of the Input/Output Slave Pending NWRITE_R Transactions register has value 0, before setting the Input/Output Slave Mapping Window 0 Control register and starting the sequence of NWRITE_R transactions.

The testbench generates a predetermined series of burst writes across the Input/Output Avalon-MM slave module's Avalon-MM write interface on the DUT. These write bursts are each converted into NWRITE_R request packets sent over the RapidIO Serial interface. The testbench cycles from 16 to 256 in steps of 8 bytes. Two tasks are invoked to carry out the burst writes, rw_addr_data and rw_data. The rw_addr_data task initiates the burst and the rw_data task completes the burst.

At the sister_rio module, the NWRITE_R request packets are received and presented across the I/O master Avalon-MM interface as write transactions. The testbench calls the sister_iom128_rd_wr_slave_bfm read_write_data task to capture the written data. The written data is checked against the expected value.

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