RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.2.2.5. LP-Serial Lane n Status 3

Table 103.  LP-Serial Lane n Status 3 — 0x21C, 0x23C, 0x25C, 0x27C
Field Bits Access Function Default
CMD changed [31] RW1C A changed cmd value in the CS field (received cmd value is different from the previously received value). 1'b0
CMD [30] RO cmd value of most recently received CS field. 1'b0
RSRV [29] RO Reserved. 1'b0
Data scrambling enabled [28] RO Value received most recently from the far end. 1'b0
Lane number in port [27:23] RO x of CS field’s Dx.y value. Should match n. This field is updated with each received CS field. 5'h00
Active port width [22:20] RO y of CS frame’s Dx.y value. This register field is updated with each received CS field. 3’b000
RSRV [19:8] RO Reserved. 12'h000
Tap(–1) Command [7:6] RO Value of this field in the most recently received CS field. 1’b0
Tap(+1) Command [5:4] RO Value of this field in the most recently received CS field. 1’b0
Reset emphasis [3] RO Value of this field in the most recently received CS field. 1’b0
Preset emphasis [2] RO Value of this field in the most recently received CS field. 1’b0
RSRV [1:0] RO Reserved. 2'b00

Did you find the information on this page useful?

Characters remaining:

Feedback Message