RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.3.2.4. Input/Output Avalon® -MM Slave Module Timing Diagrams

Both transaction requests are initiated by local user logic and appear on the Avalon® -MM interface of the slave module. Timing diagrams shows the timing dependencies on the Avalon® -MM slave interface for an outgoing RapidIO NREAD request and NWRITE transaction.
Figure 21. NREAD Transaction on the Input/Output Avalon® -MM Slave Interface
Figure 22. NWRITE Transaction on the Input/Output Avalon® -MM Slave Interface

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