RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.6.2.1. Maintenance Avalon-MM Slave

The Maintenance Avalon-MM slave module creates request packets for the Avalon-MM transaction on its slave interface and processes the response packets that it receives. Anomalies are reported through one or more of the following three channels:
  • Standard error management registers
  • Registers in the implementation defined space
  • The Avalon-MM slave interface’s error indication signal
Standard Error Management Registers
The following standard defined error types can be declared by the Maintenance Avalon-MM slave module. The corresponding error bits are then set and the required packet information is captured in the appropriate error management registers.
  • IO Error Response is declared when a response with ERROR status is received for a pending MAINTENANCE read or write request.
  • Unsolicited Response is declared when a response is received that does not correspond to any pending MAINTENANCE read or write request.
  • Packet Response Timeout is declared when a response is not received within the time specified by the Port Response Time-Out CSR for a pending MAINTENANCE read or write request.
  • Illegal Transaction Decode is declared for malformed received response packets occurring from any of the following events:
    • Response packet to pending MAINTENANCE read or write request with status not DONE nor ERROR.
    • Response packet with payload with a transaction type different from MAINTENANCE read response.
    • Response packet without payload, with a transaction type different from MAINTENANCE write response.
    • Response to a pending MAINTENANCE read request with more than 32 bits of payload (The RapidIO II IP core issues only 32-bit MAINTENANCE read requests).
Registers in the Implementation Defined Space
The Maintenance register module defines the Maintenance Interrupt register in which the following two bits report Maintenance Avalon-MM slave related error conditions:
  • WRITE_OUT_OF_BOUNDS
  • READ_OUT_OF_BOUNDS
These bits are set when the address of a write or read transfer on the Maintenance Avalon-MM slave interface falls outside of all the enabled address mapping windows. When these bits are set, the system interrupt signal mnt_mnt_s_irq is also asserted if the corresponding bit in the Maintenance Interrupt Enable register is set.
Maintenance Avalon-MM Slave Interface's Error Indication Signal

The mnt_s_readerror output signal is asserted when a response with ERROR status is received for a MAINTENANCE read request packet, when a MAINTENANCE read times out, or when the Avalon-MM read address falls outside of all the enabled address mapping windows.

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