RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.3.1.6. Processing Element Features CAR

Table 110.  Processing Element Features CAR — Offset: 0x10
Field Bits Access Function Default
Bridge [31] RO Processing element can bridge to another interface. 0
Memory [30] RO Processing element has physically addressable local address space and can be accessed as an endpoint through non-maintenance operations. This local address space may be limited to local configuration registers, on-chip SRAM, or other device. 0
Processor [29] RO Processing element physically contains a local processor or similar device that executes code. A device that bridges to an interface that connects to a processor does not count. 0
Switch [28] RO Processing element can bridge to another external RapidIO interface—an internal port to a local endpoint does not count as a switch port. 0
MULTIPORT [27] RO Processing element implements multiple external RapidIO ports. The RapidIO II IP core implements only a single RapidIO port, so this field always has the value of 1’b0. 1'b0
RSRV [26:12] RO Reserved. 25'b0
Flow Arbitration Support [11] RO Processing element supports flow arbitration. 0
RSRV [10] RO Reserved. 1'b0
Extended route table configuration support 34 [9] RO Processing element supports extended route table configuration mechanism. This property is relevant in switch processing elements only. In non-switch processing elements, it is ignored. 0
Standard route table configuration support 34 [8] RO Processing element supports standard route table configuration mechanism. This property is relevant in switch processing elements only. In non-switch processing elements, it is ignored. 0
Flow Control Support [7] RO Processing element supports flow control extensions. 0
RSRV [6] RO Reserved. 1'b0
CRF Support [5] RO Processing element supports the Critical Request Flow (CRF) indicator:
  • 1'b0 — Processing element does not support Critical Request Flow.
  • 1'b1—Processing element supports Critical Request Flow.
1'b1
LARGE_TRANSPORT [4] RO Processing element supports common transport large systems:
  • 1'b0 — Processing element does not support common transport large systems (processing element requires that the device ID width be 8 bits, and does not support a device ID width of 16 bits).
  • 1'b1 — Processing element supports common transport large systems (processing element supports a device ID width of 16 bits).
The value of this field is determined by the device ID width you select in the RapidIO II parameter editor with the Enable 16-bit device ID width setting.
0
Extended features [3] RO Processing element has extended features list; the extended features pointer is valid. 1'b1
Extended addressing support [2:0] RO Indicates the number of address bits supported by the processing element, both as a source and target of an operation. All processing elements support a minimum 34-bit address. The RapidIO II IP core supports the following valid value:
  • 3'b001 — Processing element supports 34-bit addresses.
3'b001
34 If the Extended route table configuration support bit or the Standard route table configuration support bit is set, user logic must implement the functionality and registers to support the standard or extended route table configuration. The RapidIO II IP core does not implement the Standard Route CSRs at offsets 0x70, 0x74, and 0x78.

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