RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Document Table of Contents Defining the Maintenance Address Translation Windows

Two address translation windows available for interpreting incoming Avalon-MM requests to the Maintenance module slave interface.

You must program the Tx Maintenance Window registers to support the address ranges you wish to distinguish. The RapidIO II IP core Maintenance module populates the following RapidIO Type 8 Request packet fields with values you program for the relevant address translation window:
  • prio
  • destinationID
  • hop_count
You can disable an address translation window that is available in your configuration.
The RapidIO II IP core includes one set of Tx Maintenance Mapping Window registers for each translation window. The following registers define address translation window n:
  • A base register: Tx Maintenance Mapping Window n Base
  • A mask register: Tx Maintenance Mapping Window n Mask
  • An offset register: Tx Maintenance Mapping Window n Offset
  • A control register: Tx Maintenance Mapping Window n Control
To enable a window, set the window enable (WEN) bit of the window’s Tx Maintenance Window n Mask register to the value of 1. To disable it, set the WEN bit to the value of zero.

For each defined and enabled window, the RapidIO II IP core masks out the Avalon-MM address's least significant bits with the window mask and compares the resulting address to the window base. If the address matches multiple windows, the IP core uses the lowest number matching window.

After determining the appropriate matching window, the RapidIO II IP core creates the 21-bit config_offset value in the converted MAINTENANCE transaction based on the following equation:
If (mnt_s_address[23:1] & mask[25:3]) == base[25:3]
then config_offset = (offset[23:3] & mask[23:3]) | (mnt_s_address[21:1] & ~mask[23:3])
  • mnt_s_address[23:0] is the Avalon-MM slave interface address signal, which holds bits [25:2] of the 26-bit byte address
  • mask[31:0] is the mask register
  • base[31:0] is the base address register
  • offset[23:0] is the OFFSET field of the window offset register