RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.2.1.9. Port 0 Error and Status CSR

Table 96.  Port 0 Error and Status CSR — 0x158
Field Bits Access Function Default
IDLE2_SUPPORT [31] RO Indicates whether the port supports the IDLE2 sequence for baud rates of 5.0 and below.
  • 1’b0: Port does not support the IDLE2 sequence for baud rates of 5.0 and below.
  • 1’b1: Port supports the IDLE2 sequence for baud rates of 5.0 and below.
The RapidIO II IP core currently supports only the IDLE2 sequence, so this bit always has the value of 1.
1'b1
IDLE2_ENABLE [30] RO Indicates whether the IDLE2 sequence is enabled in the RapidIO implementation for baud rates of 5.0 and below.
  • 1’b0:The IDLE2 sequence is disabled for baud rates of 5.0 and below.
  • 1’b1: The IDLE2 sequence is enabled for baud rates of 5.0 and below.
The RapidIO II IP core currently supports only the IDLE2 sequence, so this bit always has the value of 1.
1'b1
IDLE_SEQUENCE [29] RO Indicates which Idle control symbol is active.
  • 1’b0: IP core uses IDLE1 control symbols.
  • 1’b1: IP core uses IDLE2 control symbols.
The RapidIO II IP core currently supports only the IDLE2 sequence, so this bit always has the value of 1.
1'b1
RSRV [28] RO Reserved. 1'b0
FLOW_CTRL_MODE [27] R0 Indicates which flow control mode is active.
  • 1’b0: Receiver-controlled flow control is active.
  • 1’b1: Transmitter-controlled flow control is active.
1'b0
OUT_PKT_DROPD [26] RW1C Output port has discarded a packet because the failed error threshold in the Port 0 Error Rate Threshold register has been reached. After it is set, this bit is cleared only when software writes the value of 1 to it. 1'b0
OUT_FAIL_ENC [25] RW1C Output port has encountered a failed condition: the failed error threshold in the Port 0 Error Rate Threshold register has been reached. After it is set, this bit is cleared only when software writes the value of 1 to it. 1'b0
OUT_DGRD_ENC [24] RW1C Output port has encountered a degraded condition: the degraded error threshold in the Port 0 Error Rate Threshold register has been reached. After it is set, this bit is cleared only when software writes the value of 1 to it. 1'b0
RSRV [23:21] RO Reserved. 3'b0
OUT_RTY_ENC [20] RW1C Output port has encountered a retry condition. In all cases, this condition is caused by the port receiving a packet-retry control symbol. This bit is set if the OUT_RTY_STOP bit is set. 1'b0
OUT_RETRIED [19] RO Output port has received a packet-retry control symbol and cannot make forward progress. This bit is cleared when a packet-accepted or packet-not-accepted control symbol is received. 1'b0
OUT_RTY_STOP [18] RO Indicates that the output port is in the Output Retry Stopped state. Output port has been stopped due to a retry and is trying to recover. When a port receives a packet_retry control symbol, it enters the Output Retry Stopped state. In this state, the port transmits a restart-from-retry control symbol to its link partner. The link partner exits the Input Retry Stopped state and normal operation resumes. The port exits the Output Retry Stopped state. 1'b0
OUT_ERR_ENC [17] RW1C Output port has encountered a transmission error and has possibly recovered from it. This bit is set when the OUT_ERR_STOP bit is set. After it is set, this bit is cleared only when software writes the value of 1 to it. 1'b0
OUT_ERR_STOP [16] RO Indicates that the output port is in the Output Error Stopped state. Output port has been stopped due to a transmission error and is trying to recover. The following conditions cause the output port to enter this state:
  • Received an unexpected packet-accepted control symbol
  • Received an unexpected packet-retry control symbol
  • Received a packet-not-accepted control symbol
To exit from this state, the port issues an input-status link-request/input-status (restart-from-error) control symbol. The port waits for the link-response control symbol and exits the Output Error Stopped state.
1'b0
RSRV [15:11] RO Reserved. 5'b0
IN_RTY_STOP [10] RO Input port is stopped due to a retry. This bit is set when the input port is in the Input Retry Stopped state. When the receiver issues a packet-retry control symbol to its link partner, it enters the Input Retry Stopped state. The receiver issues a packet-retry when sufficient buffer space is not available to accept the packet for that specific priority. The receiver continues in the Input Retry Stopped state until it receives a restart-from-retry control symbol. 1'b0
IN_ERR_ENC [9] RW1C Input port has encountered a transmission error. This bit is set if the IN_ERR_STOP bit is set. After it is set, this bit is cleared only when software writes the value of 1 to it. 1'b0
IN_ERR_STOP [8] RO Input port is stopped due to a transmission error. The port is in the Input Error Stopped state. The following conditions cause the input port to transition to this state:
  • Cancellation of a packet by using the restart-from-retry control symbol.
  • Invalid character or valid character that does not belong in an idle sequence.
  • Single bit transmission errors.
  • Any of the following link protocol violations:
    • Acknowledgment control symbol with an unexpected packet_ackID
    • Link time-out while waiting for an acknowledgment control symbol
  • Corrupted control symbols, that is, CRC violations on the symbol.
  • Any of the following Packet Errors:
    • Unexpected ackID value
    • Incorrect CRC value
    • Invalid characters or valid non-data characters
    • Max data payload violations
The recovery mechanism consists of these steps:
  1. Issue a packet-not-accepted control symbol.
  2. Wait for link-request/input-status control symbol.
  3. Send link-response control symbol.
1'b0
RSRV [7:5] RO Reserved. 3'b0
PWRITE_PEND [4] RO This register is not implemented and is reserved. The RapidIO II IP core does not automatically issue Port-write requests, so this bit always has the value of zero. 1'b0
PORT_UNAVAIL [3] RO Indicates whether the port is available. This port is always available, so this bit always has the value of 0. 1'b0
PORT_ERR [2] RW1C This bit is set if the input port error recovery state machine encounters an unrecoverable error or the output port error recovery state machine enters the fatal_error state. The input port error recovery state machine encounters an unrecoverable error if it times out while waiting for a link-request after sending a packet-not-accepted control symbol. The output port error recovery state machine enters the fatal_error state if the following sequence of events occurs:
  1. The output port error recovery state machine enters the stop_output state when it receives a packet-not-accepted control symbol. In response, it sends the input-status link-request/input-status (restart-from-error) control symbol.
  2. One of the following events occurs in response to the link-request control symbol:
    • If the link-response is received but the ackID is outside of the outstanding ackID set, then the output port error recovery state machine enters the fatal_error state.
    • If the port times out before receiving link-response, for seven attempts to send a link-request, then the output port error recovery state machine enters the fatal_error state.
When the PORT_ERR bit is set, software determines the behavior of the RapidIO II IP core. After it is set, this bit is cleared only when software writes the value of 1 to it. The port_error output signal mirrors this register bit.
1'b0
PORT_OK [1] RO Input and output ports are initialized and can communicate with the adjacent device. This bit is asserted when the link is initialized. The value in this field appears on the port_ok output signal. 1'b0
PORT_UNINIT [0] RO Input and output ports are not initialized and are in training mode. This bit and the PORT_OK bit are mutually exclusive: at any time, at most one of them can be asserted. The RapidIO II IP core deasserts this bit when the port is initialized. 1'b1