RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.3.6.12. Port 0 Attributes Capture

Table 164.  Port 0 Attributes Capture CSR — Offset: 0x348
Field Bits Access Function Default
INFO_TYPE [31:29] RO Indicates the type of information logged. The RapidIO II IP core supports only the following valid values for this field:
  • 3’b000: Packet.
  • 3’b011: Long control symbol.
  • 3’b100: Implementation specific.
3'b000
ERROR_TYPE [28:24] RO The encoded value of the bit in the Port 0 Error Detect CSR that describes the error captured in the Port 0 Packet/Control Symbol Capture 0–3 CSRs. The encoding is 31 minus the binary number that represents the bit position in the CSRs. 5'h0
IMPL_DEPENDENT [23:8] RO The RapidIO II IP core uses this field as recommended in the RapidIO v2.2 specification.

If the value of the INFO_TYPE field is 3’b000, indicating a packet, this field captures the control bits of the first 16 packet characters.

If the value of the INFO_TYPE field is 3’b011, indicating a long control symbol, bits [23:16] of this field capture the eight control bits of the delimited long control symbol.

If the value of the INFO_TYPE field is 3’b100, indicating implementation-specific information, this field is undefined.

16'h0000
RSRV [7:1] RO Reserved. 7'h0
CAPTURE_VALID_INFO [0] RW Indicates that the Port 0 Packet/Control Symbol Capture 0–3 CSRs, and the other bits in the Port 0 Attributes Capture CSR contain valid information and are locked. To reset this bit and unlock the other fields in this register, you must write the value of 1’b0 to the CAPTURE_VALID_INFO bit.

If INFO_TYPE is 3’b011, Long control symbol, only the Port 0 Packet/Control Symbol Capture 0 CSR has valid information when these registers are locked. If INFO_TYPE is 3’b100, Implementation specific, none of these registers has valid information when they are locked. However, the CAPTURE_VALID_INFO bit is asserted when the registers are locked.

1'b0

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