RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.6.1.2. Fatal Errors

Software determines the behavior of the RapidIO II IP core following a fatal error. For example, you can program software to optionally perform any of the following actions, among others:
  • Set the PORT_DIS bit of the Port 0 Control CSR to force the initialization state machine to the SILENT state.
  • Write to the OUTBOUND_ACKID field of the Port 0 Local AckID CSR to specify the next outbound and expected packet ackID from the RapidIO link partner. You can use this option to force retransmission of outstanding unacknowledged packets.
  • Set the CLR_OUTSTANDING_ACKIDS field of the Port 0 Local AckID CSR to clear the queue of outstanding unacknowledged packets.
If the link partner is reset when its expected ackID is not zero, a fatal error occurs when the link partner receives the next transmitted packet because the link partner’s expected ackID is reset to zero, which causes a mismatch between the transmitted ackID and the expected ackID. When that occurs, you can use the Port 0 Local AckID CSR to resynchronize the expected and transmitted ackID values.

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