RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.3.2.1.4. Input/Output Avalon-MM Master Module Timing Diagrams

The RapidIO II IP core receives both transaction requests on the RapidIO link and sends them to the Logical layer Avalon-MM master module. Timing diagrams shows the timing dependencies on the Avalon-MM master interface for an incoming RapidIO NREAD and NWRITE transaction.
Figure 13. NREAD Transaction on the Input/Output Avalon-MM Master Interface
Figure 14. NWRITE Transaction on the Input/Output Avalon-MM Master Interface

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