RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.3. Logical Layer Interfaces

This section describes the features of the Logical layer module interfaces and how your system can interact with these interfaces to communicate with a RapidIO link partner.
The Logical layer consists of the following optional modules:
  • I/O slave and master modules that initiate and terminate NREAD, NWRITE, SWRITE, and NWRITE_R transactions.
  • Maintenance module that initiates and terminates MAINTENANCE transactions.
  • Doorbell module that transacts RapidIO DOORBELL messages.
  • Avalon-ST pass-through interface for implementing your own custom Logical layer logic.
In addition, the Logical layer provides an Avalon-MM slave interface called the Register Access interface which provides access to all of the RapidIO II IP core registers except the Doorbell Logical layer registers. This interface is present in all RapidIO II IP core variations.
Figure 10. Functional Block Diagram with all of the Logical Layer Modules

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