RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Document Table of Contents

7.3. Testbench Completion

The testbench concludes by checking that all of the packets have been received. If no error is detected and all packets are received, the testbench issues a TESTBENCH PASSED message stating that the simulation was successful.

If an error is detected, a TESTBENCH FAILED message is issued to indicate that the testbench has failed. A TESTBENCH INCOMPLETE message is issued if the expected number of checks is not made. For example, this message is issued if not all packets are received before the testbench is terminated. The variable tb_rio.exp_chk_cnt determines the number of checks done to ensure completeness of the testbench.

To generate a value change dump file called dump.vcd for all viewable signals, uncomment the line //$dumpvars(0,tb_rio) in the tb_rio.sv file.