RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Document Table of Contents Response to a DOORBELL Request

After the IP core detects a write to the Tx Doorbell register, internal control logic generates and sends a Type 10 packet based on the information in the Tx Doorbell and Tx Doorbell Control registers. A copy of the outbound DOORBELL packet is stored in the Acknowledge RAM.

When the IP core receives a response to an outbound DOORBELL message, the IP core writes the corresponding copy of the outbound message to the Tx Doorbell Completion FIFO (if enabled), and generates an interrupt (if enabled) on the Avalon- MM slave interface by asserting the drbell_s_irq signal of the Doorbell module. The ERROR_CODE field in the Tx Doorbell Completion Status register indicates successful or error completion.

The IP core sets the corresponding interrupt status bit each time it receives a valid response packet. The interrupt bit resets itself when the Tx Completion FIFO is empty. Software optionally can clear the interrupt status bit by writing a 1 to this specific bit location of the Doorbell Interrupt Status register.

Upon detecting the interrupt, software can fetch the completed message and determine its status by reading the Tx Doorbell Completion register and Tx Doorbell Completion Status register respectively.

An outbound DOORBELL message is assigned a time-out value based on the VALUE field of the Port Response Time-Out Control register and a free-running counter. When the counter reaches the time-out value, if the DOORBELL transaction has not yet received a response, the transaction times out.

An outbound message that times out before the IP core receives its response is treated in the same manner as an outbound message that receives an error response: if the TX_CPL field of the Doorbell Interrupt Enable register is set, the Doorbell module generates an interrupt by asserting the drbell_s_irq signal, and setting the ERROR_CODE field in the Tx Doorbell Completion Status register to indicate the error.

If the interrupt is not enabled, the Avalon-MM master must periodically poll the Tx Doorbell Completion Status register to check for available completed messages before retrieving them from the Tx Completion FIFO.

DOORBELL request packets for which RETRY responses are received are resent by hardware automatically. No retry limit is imposed on outbound DOORBELL messages.