RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.3.2.1.2. Defining the Input/Output Avalon-MM Master Address Mapping Windows

When you specify the value for Number of Rx address translation windows in the RapidIO II parameter editor, you determine the number of address translation windows available for translating incoming RapidIO read and write transactions to Avalon-MM requests on the I/O Logical layer Master port.

You must program the Input/Output Master Mapping Window registers to support the address ranges you wish to distinguish. You can disable an address translation window that is available in your configuration, but the maximum number of windows you can program is the number you specify in the RapidIO II parameter editor with the Number of Rx address translation windows value.

The RapidIO II IP core includes one set of Input/Output Master Mapping Window registers for each translation window. The following registers define address translation window n:
  • A base register: Input/Output Master Mapping Window n Base
  • A mask register: Input/Output Master Mapping Window n Mask
  • An offset register: Input/Output Master Mapping Window n Offset

You can change the values of the window defining registers at any time. You should disable a window before changing its window defining registers.

To enable a window, set the window enable (WEN) bit of the window’s Input/Output Master Mapping Window n Mask register to the value of 1. To disable it, set the WEN bit to the value of zero.

For each defined and enabled window, the RapidIO II IP core masks out the RapidIO address's least significant bits with the window mask and compares the resulting address to the window base.

The matching window is the lowest numbered window for which the following equation holds:
(rio_addr[33:4] & {xamm[1:0], mask[31:4]}) == ({xamb[1:0], base[31:4]} & {xamm[1:0], mask[31:4]})
where:
  • rio_addr[33:0] is the 34-bit RapidIO address composed of {xamsbs[1:0],address[28:0],3b’000} for RapidIO header fields xamsbs and address.
  • mask[31:0] is composed of {Mask register[31:4], 4b’0000}.
  • base[31:0] is composed of {Base register[31:4], 4b’0000}.
  • xamm[1:0] is the XAMM field of the I/O Master Mapping Window n Mask register.
  • xamb[1:0] is the XAMB field of the I/O Master Mapping Window n Base register.
The RapidIO II IP core determines the Avalon-MM address from the least significant bits of the RapidIO address and the matching window offset using the following equation:
Avalon-MM address[31:4] = (offset[31:4] & mask[31:4]) | (rio_addr[31:4] & ~mask[31:4])
where:
  • offset[31:0] is the offset register. The least significant four bits of this register are always 4’b0000.
  • The definitions of all other terms in the equation appear in the definition of the matching window.
The value of the Avalon-MM address[3:0] is always zero, because the address is a byte address and the I/O Logical layer master interface has a 128-bit wide datapath.
If the address does not match any window the I/O Logical layer Master module performs the following actions:
  • Sets the Illegal Transaction Decode Error bit in the Error Management Extension registers.
  • Sets the ADDRESS_OUT_OF_BOUNDS interrupt bit in the Input/Output Master Interrupt register.
  • Asserts the interrupt signal io_m_mnt_irq if this interrupt is enabled by the corresponding bit in the Input/Output Master Interrupt Enable register.
  • For a received NREAD or NWRITE_R request packet that does not match any enabled window, returns a RapidIO ERROR response packet.
User logic can clear an interrupt by writing 1 to the interrupt register’s corresponding bit location.
Figure 12. I/O Master Window Translation

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