RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.3.5.3.1. User Sending Write Request

Table 39.  Avalon-ST Pass-Through Interface Usage Example: Sending Write Request
User Operation Operation Type RapidIO Transaction Priority Device ID Width Payload Size (Bytes)
Send write request Tx NWRITE 0 8 40
In the first clock cycle of the example, the IP core asserts gen_tx_ready to indicate it is ready to sample data. In the same cycle, user logic asserts gen_tx_valid. Because both gen_tx_ready and gen_tx_valid are asserted, this clock cycle is an Avalon-ST ready cycle. The user logic provides valid data on gen_tx_data for the IP core to sample, and asserts gen_tx_startofpacket to indicate the current value of gen_tx_data is the initial piece of the current packet (the start of packet). On gen_tx_packet_size, user logic reports the full length of the packet is 0x32, which is decimal 50, because the packet comprises 10 bytes of header and 40 bytes of payload data.
Figure 28. Avalon-ST Pass-Through Interface NWRITE Transmit Example
The user logic provides the 40-byte payload and 10-byte header on the same bus, gen_tx_data[127:0]. Transferring these 50 bytes of information requires four clock cycles. During all of these cycles, the IP core holds gen_tx_ready high and user logic holds gen_tx_valid high, indicating the cycles are all Avalon-ST ready cycles. In the second and third cycles, user logic holds gen_tx_startofpacket and gen_tx_endofpacket low, because the information on gen_tx_data is neither start of packet nor end of packet data. In the fourth clock cycle, user logic asserts gen_tx_endofpacket and sets gen_tx_empty to the value of 0xE to indicate that only two of the bytes of data available on gen_tx_data in the current clock cycle are valid. The initial ten bytes of the packet contain header information.
Table 40.  NWRITE Request Transmit Example: RapidIO Header Fields on the gen_tx_data Bus
Field gen_tx_data Bits Value Comment
ackID [127:122] 6'h00 Value is a don’t care, because it is overwritten by the Physical layer ackID value before the packet is transmitted on the RapidIO link.
VC [121] 0 The RapidIO II IP core supports only VC0.
CRF [120] 0 This bit sets packet priority together with prio if CRF is supported. This bit is reserved if VC=0 and CRF is not supported.
prio[1:0] [119:118] 2'b00 Specifies packet priority.
tt[1:0] [117:116] 2'b00 The value of 0 indicates 8-bit device IDs.
ftype[3:0] [115:112] 4'b0101 The value of 5 indicates a Write Class packet.
destinationId[7:0] [111:104] 8'hDD Indicates the ID of the target.
sourceId[7:0] [103:96] 8'hAA Indicates the ID of the source.
ttype[3:0] [95:92] 4'b0100 The value of 4 indicates an NWRITE transaction.
size[3:0] [91:88] 4'b1100 The size and wdptr values encode the maximum size of the payload field.
transactionID[7:0] [87:80] 8'h00 Not used for NWRITE transactions.
address[28:0] [79:51] {28’hFEDCBA9, 1’b0}  
wdptr [50] 1 The size and wdptr values encode the maximum size of the payload field.
xamsbs[1:0] [49:48] 2’b00 Specifies most significant bits of extended address. Further extends the address specified by the address fields by 2 bits.

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