RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

2.5. RapidIO II IP Core Testbench Files

The RapidIO II IP core testbench is generated when you create a simulation model of the IP core.

For Intel® Arria® 10, Intel® Stratix® 10 and Intel® Cyclone® 10 GX variations:
  • The testbench script appears in <your_ip>/sim/<vendor>.
  • The testbench files appear in <your_ip>/altera_rapidio2_<version>/sim/tb.
  • The IP core simulation files appear in <Qsys_system or your_ip>/altera_rapidio2_<version>/sim/<vendor>.
For all other device variations you generate from the Intel® Quartus® Prime IP Catalog:
  • The testbench script appears in <your_ip>_sim/<vendor>.
  • The testbench files appear in <your_ip>_sim/altera_rapidio2/tb.
  • The IP core simulation files appear in <your_ip>_sim/altera_rapidio2/<vendor>.
For all other device variations you generate from the Platform Designer IP Catalog in the Intel® Quartus® Prime software:
  • The testbench script appears in <Qsys_system or your_ip>/simulation/<vendor>.
  • The testbench files appear in <Qsys_system or your_ip>/simulation/submodules/tb.
  • The IP core simulation files appear in <Qsys_system or your_ip>/simulation/submodules/<vendor>.
The RapidIO II IP core does not generate an example design.

Did you find the information on this page useful?

Characters remaining:

Feedback Message