RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.3.2.1.1. Input/Output Avalon-MM Master Interface Signals5.3.1.2. Input/Output Avalon-MM Master Interface Signals

Table 63.  Input/Output Avalon-MM Master Interface Signals
Signal Direction Description
iom_rd_wr_waitrequest Input I/O Logical Layer Avalon-MM Master module wait request.
iom_rd_wr_write Output I/O Logical Layer Avalon-MM Master module write request.
iom_rd_wr_read Output I/O Logical Layer Avalon-MM Master module read request.
iom_rd_wr_address[31:0] Output I/O Logical Layer Avalon-MM Master module address bus.
iom_rd_wr_writedata[127:0] Output I/O Logical Layer Avalon-MM Master module write data bus.
iom_rd_wr_byteenable[15:0] Output I/O Logical Layer Avalon-MM Master module byte enable.
iom_rd_wr_burstcount[4:0] Output I/O Logical Layer Avalon-MM Master module burst count.
iom_rd_wr_readresponse Input I/O Logical Layer Avalon-MM Master module read error response.
iom_rd_wr_readdata[127:0] Input I/O Logical Layer Avalon-MM Master module read data bus.
iom_rd_wr_readdatavalid Input I/O Logical Layer Avalon-MM Master module read data valid.
The I/O Avalon-MM Master module supports an interrupt line, io_m_mnt_irq, on the Register Access interface. When enabled, the following interrupts assert the io_m_mnt_irq signal:
  • Address out of bounds

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