RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.3.5.3. I/O Slave Interrupts

These interrupt bits assert the io_s_mnt_irq signal if the corresponding interrupt bit is enabled. Following are the available Input/Output slave interrupts and corresponding interrupt enable bits.
Table 148.  Input/Output Slave Interrupt — Offset: 0x10500
Field Bits Access Function Default
RSRV [31:6] RO Reserved. 26'h0
INVALID_READ_BURSTCOUNT [5] RW1C Read burst count invalid. Asserted when io_s_burstcount has a value that is larger than 16 in an Avalon-MM read request on the I/O Logical slave interface. 1'b0
INVALID_READ_BYTEENABLE [4] RW1C Read byte enable invalid. Asserted when io_s_byteenable is set to an invalid value in an Avalon-MM read request on the I/O Logical slave interface. 1'b0
INVALID_WRITE_BYTEENABLE [3] RW1C Write byte enable invalid. Asserted when io_s_byteenable is set to an invalid value in an Avalon-MM write request on the I/O Logical slave interface. 1'b0
INVALID_WRITE_BURSTCOUNT [2] RW1C Write burst count invalid. Asserted when io_s_burstcount has a value that is larger than 16, except in cases with first byteenable with a value of 0xFF00 and final byteenable with a value of 0x00FF, in an Avalon-MM write request on the I/O Logical slave interface. 1'b0
WRITE_OUT_OF_BOUNDS [1] RW1C Write request address out of bounds. Asserted when the Avalon-MM address does not fall within any enabled address mapping window. 1'b0
READ_OUT_OF_BOUNDS [0] RW1C Read request address out of bounds. Asserted when the Avalon-MM address does not fall within any enabled address mapping window. 1'b0
Table 149.  Input/Output Slave Interrupt Enable — Offset: 0x10504
Field Bits Access Function Default
RSRV [31:6] RO Reserved. 26'h0
INVALID_READ_BURSTCOUNT [5] RW Read burst count invalid interrupt enable. 1'b0
INVALID_READ_BYTEENABLE [4] RW Read byte enable invalid interrupt enable. 1'b0
INVALID_WRITE_BYTEENABLE [3] RW Write byte enable invalid interrupt enable. 1'b0
INVALID_WRITE_BURSTCOUNT [2] RW Write burst count invalid interrupt enable. 1'b0
WRITE_OUT_OF_BOUNDS [1] RW Write request address out of bounds interrupt enable. 1'b0
READ_OUT_OF_BOUNDS [0] RW Read request address out of bounds interrupt enable. 1'b0

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