RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.3.2.3. Processing Element Logical Layer Control CSR

Table 118.  Processing Element Logical Layer Control CSR — Offset: 0x4C
Field Bits Access Function Default
RSRV [31:28] RO Reserved. 29'b0
EXT_ADDR_CTRL [2:0] RO Controls the number of address bits generated by the Processing element as a source and processed by the Processing element as the target of an operation.
  • 3'b100 – Processing element supports 66 bit addresses
  • 3'b010 – Processing element supports 50 bit addresses
  • 3'b001 – Processing element supports 34 bit addresses
All other values are reserved. The RapidIO II IP core supports only 34-bit addresses, so the value of this field is always 3’b001.
3'b001

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