RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

2.6. Simulating IP Cores

The Intel® Quartus® Prime software supports RTL and gate-level design simulation of Intel® FPGA IP cores in supported EDA simulators4. Simulation involves setting up your simulator working environment, compiling simulation model libraries, and running your simulation.

You can use the functional simulation model and the testbench generated with your IP core for simulation. The functional simulation model and testbench files are generated in a project subdirectory. This directory may also include scripts to compile and run the testbench. For a complete list of models or libraries required to simulate your IP core, refer to the scripts generated with the testbench. You can use the Intel® Quartus® Prime NativeLink feature to automatically generate simulation files and scripts. NativeLink launches your preferred simulator from within the Intel® Quartus® Prime software.

Note: The Intel® Quartus® Prime Pro Edition software does not support NativeLink RTL simulation.
4 The Aldec Riviera-PRO simulator is not supported for this IP core.

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