RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Document Table of Contents User Receiving Streaming Write Request

Table 51.  Avalon-ST Pass-Through Interface Usage Example: Receive SWRITE Request
User Operation Operation Type RapidIO Transaction Priority Device ID Width Payload Size (Bytes)
Receive streaming write request Rx SWRITE 3 8 40
In the first clock cycle of the example, user logic asserts gen_rx_hd_ready and gen_rx_pd_ready, and the IP core asserts gen_rx_hd_valid and gen_rx_pd_valid, indicating it is providing valid data on gen_rx_hd_data and gen_rx_pd_data, respectively. The assertion of both the ready signal and the valid signal on each of the header and payload-data Avalon-ST interfaces makes the current cycle an Avalon-ST ready cycle for both header and data.
Figure 35. Avalon-ST Pass-Through Interface SWRITE Receive Example
The IP core asserts gen_rx_pd_startofpacket to indicate the current cycle is the first valid data cycle of the packet. In this clock cycle, the IP core also makes the header and the first 128 bits of payload data available on gen_rx_hd_data and gen_rx_pd_data, respectively. The 40-byte payload requires 3 clock cycles. In the third clock cycle of data transfer, the IP core asserts gen_rx_pd_endofpacket to indicate this is the final clock cycle of data transfer, and specifies in gen_rx_pd_empty that in the current clock cycle, the four least significant two-byte segments (the least significant eight bytes) of gen_rx_pd_data are not valid. Following the clock cycles in which valid data is available on gen_rx_pd_data, the IP core deasserts gen_rx_pd_valid.
Table 52.  SWRITE Request Receive Example: RapidIO Header Fields in gen_rx_hd_data Bus
Field gen_rx_hd_data Bits Value Comment
pd_size[8:0] [114:106] 9’h028 Payload data size is 0x28 (decimal 40).
VC [105] 0 The RapidIO II IP core supports only VC0.
CRF [104] 0 This bit sets packet priority together with prio if CRF is supported. This bit is reserved if VC=0 and CRF is not supported.
prio[1:0] [103:102] 2'b11 Specifies packet priority.
tt[1:0] [101:100] 2'b00 The value of 0 indicates 8-bit device IDs.
ftype[3:0] [99:96] 4'b0110 The value of 6 indicates a Streaming-Write Class packet.
destinationId[15:0] [95:80] 16’h00DD For variations with an 8-bit device ID, bits [95:88] (bits [15:8] of the destinationID) are set to 8’h00.
sourceId[15:0] [79:64] 16'h00AA For variations with an 8-bit device ID, bits [79:72] (bits [15:8] of the sourceID) are set to 8’h00.
address[28:0] [63:35] {28’h0AABBCC, 1’b1}  
Reserved [34] 1'b0  
xamsbs[1:0] [33:32] 2’b00 Specifies most significant bits of extended address. Further extends the address specified by the address fields by 2 bits.
Reserved[31:0] [31:0] 32’h00000000  

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