RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.5.1. Low-level Interface Receiver

The receiver in the low-level interface receives the input from the RapidIO interface, and performs the following tasks:
  • Separates packets and control symbols.
  • Removes IDLE2 idle sequence characters.
  • Detects multicast-event and stomp control symbols.
  • Detects packet-size errors.
  • Checks the control symbol 13-bit CRC and asserts symbol_error if the CRC is incorrect.

The receiver transceiver is an embedded Transceiver Native PHY IP core.

The Physical layer checks the CRC bits in an incoming RapidIO packet and flags CRC and packet size errors. It strips all CRC bits and padding bytes from the data it sends to the Transport layer.

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