RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.2. Clocking and Reset Structure

All RapidIO II IP core variations have the following clock inputs:
  • Avalon® system clock (sys_clk)
  • Reference clock for the transceiver Tx PLL and Rx PLL (tx_pll_refclk). In Intel® Arria® 10 and Intel® Cyclone® 10 GX variations, this clock port drives only the Rx PLL
  • Transceiver channel clocks (tx_bonding_clocks_chN). The RapidIO II IP core provides the following two clock outputs from the transceiver
  • Recovered data clock (rx_clkout)
  • Transceiver transmit-side clock (tx_clkout)
In addition, if you turn on Enable transceiver dynamic reconfiguration in the RapidIO II parameter editor, the IP core includes a reconfig_clk_chN input clock to clock the Intel® Arria® 10, Intel® Stratix® 10 or Intel® Cyclone® 10 GX Native PHY dynamic reconfiguration interface for each lane N.

The RapidIO II IP core can accommodate a difference of ±200 ppm between the tx_clkout and rx_clkout clocks.

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