4.2. Clocking and Reset Structure
- Avalon® system clock (sys_clk)
- Reference clock for the transceiver Tx PLL and Rx PLL (tx_pll_refclk). In Intel® Arria® 10 and Intel® Cyclone® 10 GX variations, this clock port drives only the Rx PLL
- Transceiver channel clocks (tx_bonding_clocks_chN). The RapidIO II IP core provides the following two clock outputs from the transceiver
- Recovered data clock (rx_clkout)
- Transceiver transmit-side clock (tx_clkout)
The RapidIO II IP core can accommodate a difference of ±200 ppm between the tx_clkout and rx_clkout clocks.
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