RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

5.4.1. Error Reporting Signals

Table 75.  Error Reporting Signals
Signal Direction Description
logical_transport_error Output Asserted when an error is logged in the Logical/Transport Layer Error Detect CSR at offset 0x308, and this error is enabled for reporting in the Logical/Transport Layer Error Enable CSR at offset 0x30C. If the LOG_TRANS_ERR_IRQ_EN bit in the Port 0 Control CSR at offset 0x15C has the value of 1’b1 when this signal is raised, the RapidIO II IP core asserts the std_reg_mnt_irq interrupt signal. This signal remains asserted until the Logical/Transport Layer Error Detect CSR at offset 0x308 is unlocked by user logic writing the value of 0 to the register.
port_failed Output This signal is available to report link status to the system host. The signal is asserted when the Error Rate Failed Threshold trigger ERR_RATE_FAILED_THRESHOLD field of the Port 0 Error Rate Threshold CSR at offset 0x36C is enabled (is non-zero) and this value is reached. If the PORT_FAIL_IRQ_EN bit in the Port 0 Control CSR at offset 0x15C has the value of 1’b1 when this signal is raised, the RapidIO II IP core asserts the std_reg_mnt_irq interrupt signal.
port_degraded Output This signal is available to report link status to the system host. The signal is asserted when the Error Rate Degraded Threshold trigger ERR_RATE_DEGR_THRESHOLD field of the Port 0 Error Rate Threshold CSR at offset 0x36C is enabled (is non-zero) and this value is reached. If the PORT_DEGR_IRQ_EN bit in the Port 0 Control CSR at offset 0x15C has the value of 1’b1 when this signal is raised, the RapidIO II IP core asserts the std_reg_mnt_irq interrupt signal.

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