RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.3.2.2.3. Defining the Input/Output Avalon-MM Slave Address Mapping Windows

When you specify the value for Number of Tx address translation windows in the RapidIO II parameter editor, you determine the number of address translation windows available for translating incoming Avalon-MM read and write transactions to RapidIO read and write requests.

You must program the Input/Output Slave Mapping Window registers to support the address ranges you wish to distinguish. You can disable an address translation window that is available in your configuration, but the maximum number of windows you can program is the number you specify in the RapidIO II parameter editor with the Number of Tx address translation windows value.

The RapidIO II IP core includes one set of Input/Output Slave Mapping Window registers for each translation window. The following registers define address translation window n:
  • A base register: Input/Output Slave Mapping Window n Base
  • A mask register: Input/Output Slave Mapping Window n Mask
  • An offset register: Input/Output Slave Mapping Window n Offset
  • A control register: Input/Output Slave Mapping Window n Control
The control register stores information the RapidIO II IP core uses to prepare the RapidIO packet header, including the target device’s destination ID, the request packet's priority, and to select between the three available write request packet types: NWRITE, NWRITE_R and SWRITE.

You can change the values of the window defining registers at any time, even after sending a request packet and before receiving its response packet. However, you should disable a window before changing its window defining registers.

To enable a window, set the window enable (WEN) bit of the window’s Input/Output Slave Mapping Window n Mask register to the value of 1. To disable it, set the WEN bit to the value of zero.

For each defined and enabled window, the RapidIO II IP core masks out the RapidIO address's least significant bits with the window mask and compares the resulting address to the window base.

The matching window is the lowest numbered window n for which the following equation holds:
(ios_rd_wr_addr[31:4] & mask[31:4]) == (base[31:4] & mask[31:4])
where:
  • ios_rd_wr_addr[31:0] is the I/O Logical layer Avalon-MM slave address bus. If the field has fewer than 32 bits, the IP core pads the actual bus value with leading zeroes for the matching comparison.
  • mask[31:4] is the MASK field of the Input/Output Slave Mapping Window n Mask register.
  • base[31:4] is the BASE field of the Input/Output Slave Mapping Window n Base register.
The RapidIO II IP core determines the value for the RapidIO packet header xamsbs and address fields from the least significant bits of the Avalon-MM ios_rd_wr_address signal and the matching window offset using the following equation:
rio_addr [33:4] = {xamo, ((offset [31:4] & mask [31:4]) | ios_rd_wr_address[31:4])}
where:
  • rio_addr[33:0] is the 34-bit RapidIO address composed of {xamsbs[1:0],address[28:0],3b’000} for RapidIO header fields xamsbs and address.
  • xamo[1:0] is the XAMO field of the Input/Output Slave Mapping Window n Offset register.
  • offset[31:4] is the OFFSET field of the Input/Output Slave Mapping Window n Offset register.
  • The definitions of all other terms in the equation appear in the definition of the matching window.
If the address does not match any window the I/O Logical layer Slave module performs the following actions:
  • Sets the WRITE_OUT_OF_BOUNDS or READ_OUT_OF_BOUNDS interrupt bit in the Input/Output Slave Interrupt register.
  • Asserts the interrupt signal io_s_mnt_irq if this interrupt is enabled by the corresponding bit in the Input/Output Slave Interrupt Enable register.
  • Increments the COMPLETED_OR_CANCELLED_WRITES field of the Input/Output Slave RapidIO Write Requests register if the transaction is a write request.
User logic can clear an interrupt by writing 1 to the interrupt register’s corresponding bit location.

The Avalon-MM slave interface burstcount and byteenable signals determine the values of the RapidIO packet header fields wdptr and rdsize or wrsize.

The RapidIO II IP core copies the values you program in the PRIORITY and DESTINATION_ID fields of the control register for the matching window, to the RapidIO packet header fields prio and destinationID, respectively.

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