RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.3.1.1. Non-Doorbell Register Access Operations

The RapidIO II IP core registers are 32 bits wide and are accessible only on a 32-bit (4-byte) basis. The addressing for the registers therefore increments by units of 4.

The Register Access interface supports simple reads and writes with variable latency. The interface provides access to 32-bit words addressed by a 22-bit wide word address, corresponding to a 24-bit wide byte address. This address space provides access to the entire RapidIO configuration space, including any user-defined registers.

A local host can access the RapidIO II IP core registers through the Register Access Avalon-MM slave interface.

If your RapidIO II IP core variation includes a Maintenance module, a remote host can access the RapidIO II IP core registers by sending MAINTENANCE transactions targeted to this local RapidIO II IP core. If the transaction is a read or write to an address in the IP core register address range, the RapidIO II IP core routes the transaction to the appropriate register internally. If the transaction is a read or write to an address outside the address ranges of the Logical layer modules instantiated in the RapidIO II IP core, the IP core routes the transaction to user logic through the Maintenance master interface.

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