RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.3.6.7. Logical/Transport Layer Control Capture

Table 159.  Logical/Transport Layer Control Capture CSR — Offset: 0x31C
Field Bits Access Function Default
FTYPE 44 [31:28] RO Format type associated with the error. 4'h0
TTYPE 45 [27:24] RO Transaction type associated with the error. 4'h0
MSG_INFO 46 [23:16] RO Letter, mbox, and msgseg for the last message request received for the mailbox that had an error. 8'h00
Implementation Specific [15:0] RO Reserved for this implementation. 16'h0000
44 For errors the RapidIO II IP core does not detect internally, set this field using the capture_ftype_wr and capture_ftype_in input signals.
45 For errors the RapidIO II IP core does not detect internally, set this field using the capture_ttype_wr and capture_ttype_in input signals.
46 For errors the RapidIO II IP core does not detect internally, set this field using the letter_wr, mbox_wr, msgseg_wr, and xmbox_wr, and letter_in, mbox_in, msgseg_in, and xmbox_in input signals.

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