RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.6.2.5. Input/Output Avalon-MM Slave

The I/O Avalon-MM slave module creates request packets for the Avalon-MM transaction on its read and write slave interfaces and processes the response packets that it receives. Anomalies are reported through one or more of the following three channels:
  • Standard error management registers
  • Registers in the implementation defined space
  • The Avalon-MM slave interface's error indication signal
Standard Error Management Registers
The following standard defined error types can be declared by the I/O Avalon-MM slave module. The corresponding error bits are then set and the required packet information is captured in the appropriate error management registers.
  • IO Error Response is declared when a response with ERROR status is received for a pending NREAD or NWRITE_R request.
  • Unsolicited Response is declared when a response is received that does not correspond to any pending NREAD or NWRITE_R request.
  • Packet Response Time-Out is declared when a response is not received within the time specified by the Port Response Time-Out Response CSR for an NREAD or NWRITE_R request.
  • Illegal Transaction Decode is declared for malformed received response packets occurring from any of the following events:
    • NREAD or NWRITE_R response packet with status not DONE nor ERROR.
    • NWRITE_R response packet with payload or with a transaction type indicating the presence of a payload.
    • NREAD response packet without payload, with incorrect payload size, or with a transaction type indicating absence of payload.
Registers in the Implementation Defined Space
The I/O Avalon-MM slave module defines the Input/Output Slave Interrupt registers with the following bits:
  • INVALID_READ_BURSTCOUNT
  • INVALID_READ_BYTEENABLE
  • INVALID_WRITE_BYTEENABLE
  • INVALID_WRITE_BURSTCOUNT
  • WRITE_OUT_OF_BOUNDS
  • READ_OUT_OF_BOUNDS
When any of these bits are set, the system interrupt signal io_s_mnt_irq is also asserted if the corresponding bit in the Input/Output Slave Interrupt Enable register is set.
The Avalon-MM Slave Interface's Error Indication Signal

The ios_rd_wr_readresponse output is asserted when a response with ERROR status is received for an NREAD request packet, when an NREAD request times out, or when the Avalon-MM address falls outside of the enabled address mapping window. As required by the Avalon-MM interface specification, a burst in which the ios_rd_wr_readresponse signal is asserted completes despite the error signal assertion.

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