RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
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4.6.2. Logical Layer Error Management

The Logical layer modules only need to process Logical layer errors because errors detected by the Physical layer are masked from the Logical layer module. If an errored packet arrives at the Transport layer, the Transport layer does not pass it on to the Logical layer modules.

The RapidIO specification defines the following common errors and the protocols for managing them:
  • Malformed request or response packets
  • Unexpected Transaction ID
  • Missing response (time-out)
  • Response with ERROR status
The RapidIO II IP core implements the optional Error Management Extensions as defined in Part 8 of the RapidIO Interconnect Specification Revision 2.2.

When enabled, each error defined in the Error Management Extensions triggers the assertion of an interrupt on its module-specific interrupt output signal and causes the capture of various packet header fields in the appropriate capture CSRs.

In addition to the errors defined by the RapidIO specification, each Logical layer module has its own set of error conditions that can be detected and managed.