RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.3.3.6. Handling Port-Write Transactions

The RapidIO II IP core supports RapidIO MAINTENANCE port-write transactions. However, these transactions do not appear on the Maintenance Avalon-MM interface.

Your system controls the transmission of port-write transactions on the RapidIO link by programming RapidIO II IP core transmit port-write registers using the Register Access interface. When the RapidIO II IP core receives a MAINTENANCE port-write request packet on the RapidIO link, it processes the transaction according to the values you program in the receive port-write registers, and if you have enabled this interrupt signal, asserts the mnt_mnt_s_irq signal to inform the system that the IP core has received a port-write transaction.

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