RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.2.1.10. Port 0 Control CSR

Table 97.  Port 0 Control CSR — 0x15C
Field Bits Access Function Default
PORT_WIDTH [31:30] RO Together with the EXTENDED_PORT_WIDTH field, indicates the hardware widths this port supports in addition to the 1× (single lane) width:
  • Bit [31]: 2× (two-lane) support
    • 1’b0: This port does not support a 2× RapidIO link.
    • 1’b1: This port supports a 2× RapidIO link.
  • Bit[30]: 4× (four-lane) support
    • 1’b0: This port does not support a 4× RapidIO link.
    • 1’b1: This port supports a 4× RapidIO link.
32
INIT_WIDTH [29:27] RO Width of the port after being initialized:
  • 3'b000: Single lane port, lane 0.
  • 3'b001: Single lane port, lane R (redundancy lane).
  • 3'b010: Four-lane port.
  • 3'b011: Two-lane port.
  • 3’b100: Eight-lane port.
  • 3’b101: Sixteen-lane port.
  • 3’b110–3'b111—Reserved.
This field is reset to the largest supported port width, which can be any of 3’b000, 3’b010, and 3’b011, based on your selection in the RapidIO II parameter editor.
32
PWIDTH_OVRIDE [26:24] RW Together with the EXTENDED_PWIDTH_OVRIDE field (bits [15:14]), indicates soft port configuration to control the width modes available for port initialization.
  • When bit [26] has the value of 1’b0, bits [15:14] are Reserved.
  • When bit [26] has the value of 1’b1:
    • Bit [25] is the Enable bit for 4× mode.
    • Bit [24] is the Enable bit for 2× mode.
    • Bit [15] is the Enable bit for 8× mode.
    • Bit [14] is the Enable bit for 16× mode.
The RapidIO II IP core supports the following valid values for (PWIDTH_OVRIDE,EXTENDED_PWIDTH_OVRIDE):
  • 5'b000xx—All lane widths that the port supports are enabled.
  • 5'b010xx—Force single lane, lane R not forced.
  • 5'b011xx—Force single lane, force lane R.
  • 5'b10100—2× mode is enabled, 4× mode is disabled.
  • 5’b11000—4× mode is enabled, 2× mode is disabled.
  • 5'b11100—2× and 4× modes are enabled.
All other values are Reserved. When the value in the PWIDTH_OVRIDE or EXTENDED_PWIDTH_OVRIDE field changes, the port re-initializes using the new field values.
3'b000
PORT_DIS [23] RW Port disable:
  • 'b0—Port receivers/drivers are enabled.
  • 'b1—Port receivers are disabled and are unable to receive or transmit any packets or control symbols.
While this bit is set, the initialization state machines force_reinit signal is asserted. This assertion forces the port to the SILENT state
1'b0
OUT_PENA [22] RW Output port transmit enable:
  • 'b0—Port is stopped and not enabled to issue any packets except to route or respond to I/O logical MAINTENANCE packets. Control symbols are not affected and are sent normally.
  • 'b1—Port is enabled to issue packets.
The value in the PORT_LOCKOUT field (bit [1] of this register) can override the values in the OUT_PENA and IN_PENA fields
1'b0
IN_PENA [21] RW Input port receive enable:
  • 'b0—Port is stopped and only enabled to respond to I/O Logical MAINTENANCE requests. Other requests return packet-not-accepted control symbols to force an error condition to be signaled by the sending device. However, the IP core still handles normally any control symbols it receives.
  • 'b1—Port is enabled to respond to any packet.
The value in the PORT_LOCKOUT field (bit [1] of this register) can override the values in the OUT_PENA and IN_PENA fields.
1'b0
ERR_CHK_DIS [20] RO This bit enables (1’b0) or disables (1’b1) all RapidIO transmission error checking. The RapidIO II IP core does not support the disabling of error checking and recovery, so this bit always has the value of 1’b0. 1'b0
Multicast-event Participant [19] RW Indicates that the system should send incoming Multicast-event control symbols to this port (multiple port devices only). 1'b1
Flow Control Participant [18] RW Enables or disables flow control transactions:
  • 1’b0: Do not route or issue flow control transactions to this port.
  • 1’b1: Route or issue flow control transactions to this port.
This field does not affect the IP core configuration.
32
Enumeration Boundary [17] RW Indicates whether this port should delimit enumeration. Any enumeration boundary aware system enumeration algorithm should honor this flag. The algorithm, on either the Rx port or the Tx port, should not enumerate past a port in which this bit is set to the value of 1’b1. This field supports software-enforced enumeration domains in the RapidIO network. 32
Flow Arbitration Participant [16] RW Enables or disables flow arbitration transactions:
  • 1’b0: Do not route or issue flow arbitration transactions to this port.
  • 1’b1: Route or issue flow arbitration transactions to this port.
32
EXTENDED_PWIDTH_ OVRIDE [15:14] RW Together with the PWIDTH_OVRIDE field (bits [26:24] of this register), indicates soft port configuration to control the width modes available for port initialization. Refer to the description of the PWIDTH_OVRIDE field. 2'b0
EXTENDED_PORT_ WIDTH [13:12] RO Together with the PORT_WIDTH field, indicates the hardware widths this port supports:
  • Bit [13]: 8× support
    • 1’b0: This port does not support a 8× RapidIO link.
    • 1’b1: This port supports a 8× RapidIO link.
  • Bit[12]: 16× support
    • 1’b0: This port does not support a 16× RapidIO link.
    • 1’b1: This port supports a 16× RapidIO link.
The RapidIO II IP core does not support 8-lane or 16-lane variations, so this field is always set to 2’b00.
2'b0
RSRV [11:9] RO Reserved. 3'b0
DIS_DEST_ID_CHK [8] RO This bit determines whether the RapidIO II IP core checks destination IDs in incoming request packets, or promiscuously accepts all incoming request packets with a supported ftype. The reset value is set in the RapidIO II parameter editor.
  • 1'b0: Check Destination ID.
  • 1'b1: Disable Destination ID checking.
32
LOG_TRANS_ERR_IRQ _EN [7] RW Controls whether an interrupt is generated when the logical_transport_error input signal changes from the value of 0 to the value of 1. 1'b0
PORT_ERR_IRQ_EN [6] RW Controls whether an interrupt is generated when an error is flagged in the Port 0 Error Detect register at offset 0x340. If this bit has the value of 1, an interrupt is generated when any enabled error is flagged in the Port 0 Error Detect register. 1'b0
PORT_FAIL_IRQ_EN [5] RW Controls whether an interrupt is generated when the port_failed input signal changes from the value of 0 to the value of 1. 1'b0
PORT_DEGR_IRQ_EN [4] RW Controls whether an interrupt is generated when the port_degraded input signal changes from the value of 0 to the value of 1. 1'b0
STOP_ON_PRT_FAIL_ ENCOUNTER_ENABLE [3] RW Together with the DROP_PKT_ENABLE field, specifies the behavior of the port when the failed error threshold in the Port 0 Error Rate Threshold register (offset 0x36C) has been reached or exceeded. The RapidIO II IP core supports the following valid values for (STOP_ON_PRT_FAIL_ENCOUNTER_ENABLE, DROP_PKT_ENABLE):
  • 2'b00: The port continues to attempt to transmit packets to the RapidIO link partner.
  • 2'b01: The port discards packets that receive a packet-not-accepted response. When the port discards a packet, it sets the OUT_PKT_DROPD bit in the Port 0 Error and Status CSR (offset 0x158). The port resumes normal operation when the value in the Error Rate Counter field of the Port 0 Error Rate CSR (offset 0x368) falls below the failed error threshold. This value is valid only for switch devices.
  • 2’b10: The port stops trying to send packets to the link partner, until software resets the OUT_FAIL_ENC field of the Port 0 Error and Status CSR (offset 0x158). The IP core does apply backpressure to ensure the queues do not overflow.
  • 2’b11: The port discards all output packets, until software resets the OUT_FAIL_ENC field of the Port 0 Error and Status CSR (offset 0x158). When the port discards a packet, it sets the OUT_PKT_DROPD bit in the Port 0 Error and Status CSR.
1'b0
DROP_PKT_ENABLE [2] RW Together with the STOP_ON_PRT_FAIL_ENCOUNTER_ENABLE field, specifies the behavior of the port when the failed error threshold in the Port 0 Error Rate Threshold register (offset 0x36C) has been reached or exceeded. Refer to the description of the STOP_ON_PRT_FAIL_ENCOUNTER_ENABLE field. 1'b0
PORT_LOCKOUT [1] RW This bit indicates whether the port is stopped or the IN_PENA (bit [21]) and OUT_PENA (bit [22]) register fields control the port:
  • 1'b0—The Input Port Enable (IN_PENA) and Output Port Enable (OUT_PENA) fields in this register control which packets the port may receive and transmit on the RapidIO link.
  • 1'b1—Port is stopped and is not enabled to issue or receive any packets. The input port can still follow the training procedure and can still send and respond to link-requests. All received packets return packet-not-accepted control symbols to force an error condition to be signaled by the sending device.
1'b0
PORT_TYPE [0] RO Indicates the port type, parallel or serial.
  • 1'b0: Parallel port.
  • 1'b1: Serial port.
The RapidIO II IP core supports only serial ports, so this bit always has the value of 1’b1.
1'b1
32 Reflects the selection made in the RapidIO II parameter editor.

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