RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.3.4.3. I/O Master Interrupts

The RapidIO II IP core asserts the io_m_mnt_irq signal if the interrupt bit is enabled. Following are the available Input/Output Master interrupt and corresponding interrupt enable bit.
Table 141.  Input/Output Master Interrupt — Offset: 0x103DC
Field Bits Access Function Default
RSRV [31:1] RO Reserved. 31'h0
ADDRESS_OUT_OF_BOUNDS [0] RW1C Address out of bounds. Asserted when the RapidIO address does not fall within any enabled address mapping window. 1'b0
Table 142.  Input/Output Master Interrupt Enable — Offset: 0x103FC
Field Bits Access Function Default
RSRV [31:1] RO Reserved. 31'h0
ADDRESS_OUT_OF_BOUNDS [0] RW Address out of bounds interrupt enable. 1'b0

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