RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.3.4.1. Preserving Transaction Order

If you select Prevent doorbell messages from passing write transactions in the RapidIO II parameter editor, each DOORBELL message from the Avalon-MM interface is potentially delayed in a Tx staging FIFO. After all I/O write transactions that started on the write Avalon-MM slave interface before this DOORBELL message arrived on the Doorbell module Avalon-MM interface have been transmitted to the Transport layer, the IP core releases the message from the FIFO. An I/O write transaction is considered to have started before a DOORBELL transaction if the ios_rd_wr_write signal is asserted while the ios_rd_wr_waitrequest signal is not asserted, on a cycle preceding the cycle on which the drbell_s_write signal is asserted for writing to the Tx Doorbell register while the drbell_s_waitrequest signal is not asserted.

If you do not select Prevent doorbell messages from passing write transactions in the RapidIO II parameter editor, the Doorbell Tx staging FIFO is not configured in the RapidIO II IP core.

Did you find the information on this page useful?

Characters remaining:

Feedback Message