RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

3.1.3. Transceiver Settings

Table 9.  Transceiver SettingsIn the table below, all the parameters except VCCR_GXB, VCCT_GXB, and Transceiver Tile are only available when you turn on the Enable transceiver dynamic reconfiguration parameter.
Parameter Value Device Family Software Support Description
Transceiver Tile L-Tile, H-Tile Intel® Stratix® 10 Intel® Quartus® Prime Pro Edition Specifies the transceiver tile on your target Intel® Stratix® 10 device. The Device settings of the Intel® Quartus® Prime Pro Edition project in which you generate the IP core determines the transceiver tile type.

In Intel® Quartus® Prime Pro Edition 17.1, this parameter is grayed out. The correct tile is derived when you select a device for the project. The IP generates the correct tile type for your target Intel® Stratix® 10 device.

VCCR_GXB and VCCT_GXB supply voltage for the transceivers 1.0 V, 1.1 V Intel® Stratix® 10 Intel® Quartus® Prime Pro Edition This parameter specifies the VCCR_GXB and VCCT_GXB transceiver supply voltage. The default value is 1.0 V.
Enable transceiver dynamic reconfiguration On/Off Intel® Arria® 10, Intel® Stratix® 10, and Intel® Cyclone® 10 GX Intel® Quartus® Prime Standard Edition, Intel® Quartus® Prime Pro Edition This parameter specifies that the IP core instantiates Intel® Arria® 10 or Intel® Stratix® 10 Transceiver Native PHY with dynamic reconfiguration enabled. If you do not expect to use this interface, you can turn off this parameter to lower the number of IP core signals to route.
Enable transceiver Altera Debug Master Endpoint (ADME) On/Off Intel® Arria® 10, Intel® Stratix® 10 and Intel® Cyclone® 10 GX Intel® Quartus® Prime Standard Edition, Intel® Quartus® Prime Pro Edition When you turn on this option, an embedded Altera Debug Master Endpoint connects internally to the Avalon® -MM slave interface for dynamic reconfiguration. The ADME can access the reconfiguration space of the transceiver. It uses JTAG via the System Console to run tests and debug functions.
Transceiver Share reconfiguration interface On/Off Intel® Arria® 10, Intel® Stratix® 10 and Intel® Cyclone® 10 GX Intel® Quartus® Prime Standard Edition, Intel® Quartus® Prime Pro Edition When you turn on this option, the Native PHY presents a single Avalon® -MM slave interface for dynamic reconfiguration of all channels. In this configuration, the upper address bits (for Intel® Arria® 10 devices - [log2<N> + 9:10] and for Intel® Stratix® 10 devices - [log2<N> + 10:11]) of the reconfiguration address bus specify the selected channel and the lower address bits (for Intel® Arria® 10 devices - [9:0] and for Intel® Stratix® 10 devices - [10:0]) provide the register offset address within the reconfiguration space of the selected channel. This option is unavailable in 1x mode. This option is auto-enabled when you turn on the Enable transceiver Altera Debug Master Endpoint (ADME) option.
Enable Transceiver capability registers On/Off Intel® Arria® 10, Intel® Stratix® 10 Intel® Quartus® Prime Standard Edition, Intel® Quartus® Prime Pro Edition Turn on this option to enable capability registers. These registers provide high-level information about the transceiver channel's /PLL's configuration.
Set user-defined IP identifier User-specified Intel® Arria® 10, Intel® Stratix® 10 and Intel® Cyclone® 10 GX Intel® Quartus® Prime Standard Edition, Intel® Quartus® Prime Pro Edition Sets a user-defined numeric identifier that can be read from the user_identifier offset when the capability registers are enabled.
Enable Transceiver control and status registers On/Off Intel® Arria® 10, Intel® Stratix® 10 and Intel® Cyclone® 10 GX Intel® Quartus® Prime Standard Edition, Intel® Quartus® Prime Pro Edition Turn on this option to enable soft registers for reading status signals and writing control signals on the PHY /PLL interface through the reconfiguration interface.
Enable Transceiver PRBS soft accumulators On/Off Intel® Arria® 10, Intel® Stratix® 10 and Intel® Cyclone® 10 GX Intel® Quartus® Prime Standard Edition, Intel® Quartus® Prime Pro Edition Turn on this option to enable soft logic to perform PRBS bit and error accumulation when using the hard PRBS generator and checker.

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