RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.2.6. Reset for RapidIO II IP Cores

All RapidIO II IP core variations have the following signals related to reset:
  • rst_n — resets the RapidIO II IP core
  • tx_ready, tx_analogreset, tx_digitalreset, tx_digitalreset_stat 12, tx_analogreset_stat 12 — reset the transmit side of the transceiver
  • rx_ready, rx_analogreset, rx_digitalreset, rx_digitalrest_stat 12, rx_analogreset_stat 12 — reset the receive side of the transceiver
  • pll_powerdown — reset one or more TX PLLs in the transceiver. This signal is available in Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V variations only.
In addition, if you turn on Enable transceiver dynamic reconfiguration in the RapidIO II parameter editor, the IP core includes reconfig_reset_chN input signals. For each N, the reconfig_reset_chN signal resets the Intel® Arria® 10, Intel® Stratix® 10 or Intel® Cyclone® 10 GX Native PHY dynamic reconfiguration interface for the transceiver channel that implements RapidIO lane N.
The reset sequence and requirements vary among device families. To implement the reset sequence correctly for your RapidIO II IP core, you must connect the tx_ready, tx_analogreset, tx_digitalreset, rx_ready, rx_analogreset, rx_digitalreset , tx_digitalreset_stat, tx_analogreset_stat , rx_digitalreset_stat, rx_analogreset_stat , and pll_powerdown reset signals to the Transceiver PHY Reset Controller IP core. User logic must drive the following signals from a single reset source:
  • RapidIO II IP core rst_n (active low) input signal.
  • Transceiver PHY Reset Controller IP core reset (active high) input signal.
  • TX PLL pll_powerdown (active high) input signal.
  • TX PLL mcgb_rst (active high) input signal. However, Intel® Arria® 10 and Intel® Cyclone® 10 GX device requirements take precedence. Depending on the external TX PLL configuration, your design might need to drive pll_powerdown and TX PLL mcgb_rst with different constraints.
User logic must connect the remaining input reset signals of the RapidIO II IP core to the corresponding output signals of the Transceiver PHY Reset Controller IP core.
The rst_n input signal can be asserted asynchronously, but must last at least one Avalon® system clock period and be deasserted synchronously to the rising edge of the Avalon® system clock.
Figure 8. Circuit to Ensure Synchronous Deassertion of rst_n
In systems generated by Platform Designer, this circuit is generated automatically. However, if your RapidIO II IP core variation is not generated by Platform Designer, you must implement logic to ensure the minimal hold time and synchronous deassertion of the rst_n input signal to the RapidIO II IP core.

The assertion of rst_n causes the whole RapidIO II IP core to reset. The requirement that the reset controller reset input signal and the TX PLL pll_powerdown and mcgb_rst input signals be asserted with rst_n ensures that the PHY IP core resets with the RapidIO II IP core.

User logic must assert the Transceiver PHY Reset Controller IP core reset signal with rst_n. However, each signal is deasserted synchronously with its corresponding clock.
Figure 9. Circuit to Ensure Synchronous Assertion of reset with rst_nIn this figure, clock is the Transceiver PHY Reset Controller IP core input clock. You can extend this logic as appropriate to include any additional reset signals.
In systems generated by Platform Designer, this circuit is generated automatically. However, if your RapidIO II IP core variation is not generated by Platform Designer, you must implement logic to ensure that rst_n and reset are driven from the same source, and that each meets the minimal hold time and synchronous deassertion requirements.

While the module is held in reset, the Avalon® -MM waitrequest outputs are driven high and all other outputs are driven low. When the module comes out of the reset state, all buffers are empty.

Note: You must de-assert all IP reset signals and allow link initialization to access the Command and Status Register (CSR) block.

Consistent with normal operation, following the reset sequence, the Initialization state machine transitions to the SILENT state. In this state, the transmitters are turned off.

If two communicating RapidIO II IP cores are reset one after the other, one of the IP cores may enter the Input Error Stopped state because the other IP core is in the SILENT state while this one is already initialized. The initialized IP core enters the Input Error Stopped state and subsequently recovers.

12 Only for Intel® Stratix® 10 devices.

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