RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.2. Physical Layer Registers

The RapidIO II IP core implements the following Physical layer registers in Extended Features space:
  • All of the LP-Serial Extended Features block registers.
  • The LP-Serial Lane Extended Features block for up to four lanes, including three implementation-specific registers per lane.

    The LP-Serial Lane Extended Features block implementation-specific registers support software-driven control of transmitter pre-emphasis for both the local and remote ends of the RapidIO link.

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