RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

5.3.2. Avalon® -ST Pass-Through Interface Signals

Table 68.   Avalon® -ST Pass-Through Interface Transmit Side ( Avalon® -ST Sink) SignalsAll of these signals are synchronized with the sys_clk clock.
Signal Direction Function
gen_tx_ready Output

Indicates that the IP core is ready to receive data on the current clock cycle. Asserted by the Avalon® -ST sink to mark ready cycles, which are the cycles in which transfers can take place. If ready is asserted on cycle N, the cycle (N+READY_LATENCY) is a ready cycle.

In the RapidIO II IP core, READY_LATENCY is equal to 0. This signal may alternate between 0 and 1 when the Avalon® -ST pass-through transmitter interface is idle.

gen_tx_valid Input Used to qualify all the other transmit side input signals of the Avalon® -ST pass-through interface. On every ready cycle in which gen_tx_valid is high, data is sampled by the IP core. You must assert gen_tx_valid continuously during transmission of a packet, from the assertion of gen_tx_startofpacket to the deassertion of gen_tx_endofpacket.
gen_tx_startofpacket Input Marks the active cycle containing the start of the packet. The user logic asserts gen_tx_startofpacket and gen_tx_valid to indicate that a packet is available for the IP core to sample.
gen_tx_endofpacket Input Marks the active cycle containing the end of the packet.
gen_tx_data[127:0] Input

A 128-bit wide data bus. Carries the bulk of the information transferred from the source to the sink.

The RapidIO II IP core fills in the RapidIO packet ackID field and adds the CRC bits and padding bytes, but otherwise copies the bits from gen_tx_data to the RapidIO packet without modifying them. Therefore, you must pack the appropriate RapidIO packet fields in the correct RapidIO packet format in the most significant bits of the gen_tx_data bus, gen_tx_data[127:N]. The total width (127 – N + 1) of the header fields depends on the transaction and the device ID width.

gen_tx_empty[3:0] Input This bus identifies the number of empty bytes on the final data transfer of the packet, which occurs during the clock cycle when gen_tx_endofpacket is asserted. The number of empty bytes must always be even.
gen_tx_packet_size[8:0]25 Input Indicates the number of valid bytes in the packet being transferred. The IP core samples this signal only while gen_tx_startofpacket is asserted. User logic must ensure this signal is correct while gen_tx_startofpacket is asserted.
Table 69.   Avalon® -ST Pass-Through Interface Receive Side ( Avalon® -ST Source) Data SignalsFollowing are the Avalon® -ST pass-through interface receive side payload data signals. The application should sample payload data only when both gen_rx_pd_ready and gen_rx_pd_valid are asserted.
Signal Direction Function
gen_rx_pd_ready Input Indicates to the IP core that the user’s custom logic is ready to receive data on the current cycle. Asserted by the sink to mark ready cycles, which are cycles in which transfers can occur. If ready is asserted on cycle N, the cycle (N+READY_LATENCY) is a ready cycle. The RapidIO II IP core is designed for READY_LATENCY equal to 0.
gen_rx_pd_valid Output Used to qualify all the other output signals of the receive side pass-through interface. On every rising edge of the clock during which gen_rx_pd_valid is high, gen_rx_pd_data can be sampled.
gen_rx_pd_startofpacket Output Marks the active cycle containing the start of the packet.
gen_rx_pd_endofpacket Output Marks the active cycle containing the end of the packet.
gen_rx_pd_data[127:0] Output A 128-bit wide data bus for data payload.
gen_rx_pd_empty[3:0] Output This bus identifies the number of empty two-byte segments on the 128-bit wide gen_rx_pd_data bus on the final data transfer of the packet, which occurs during the clock cycle when gen_tx_endofpacket is asserted. This signal is 4 bits wide.
Table 70.   Avalon® -ST Pass-Through Interface Receive Side ( Avalon® -ST Source) Header SignalsFollowing are the Avalon® -ST pass-through interface receive side header signals. The application should sample header data only when both gen_rx_hd_ready and gen_rx_hd_valid are asserted.
Signal Direction Function
gen_rx_hd_ready Input Indicates to the IP core that the user’s custom logic is ready to receive packet header bits on the current clock cycle. Asserted by the sink to mark ready cycles, which are cycles in which transfers can occur. If ready is asserted on cycle N, the cycle (N+READY_LATENCY) is a ready cycle. The RapidIO II IP core is designed for READY_LATENCY equal to 0.
gen_rx_hd_valid Output Used to qualify the receive side pass-through interface output header bus. On every rising edge of the clock during which gen_rx_hd_valid is high, gen_rx_hd_data can be sampled.
gen_rx_hd_data[114:0] Output A 115-bit wide bus for packet header bits. Data on this bus is valid only when gen_rx_hd_valid is high.
25 This signal is not defined in the Avalon® Interface Specifications. However, it refers to data being transferred on the Avalon® -ST sink interface.

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